Dynamic random access memory (DRAM) devices are volatile memory devices. Therefore, when power is removed from DRAM devices, the contents and operating configurations typically are not retained. Each time a DRAM device is powered up, a predefined sequence of steps is required to initialize the internal state machines of the DRAM device and to configure user-defined operating parameters.
Conventional main memory subsystems, however, rely on an external controller, such as a processor, to perform initialization operations. Accordingly, large amounts of data must typically be communicated back and forth between the controller and memory to perform initialization. Due to this arrangement, initialization causes high latency as large amounts of data are transferred over the memory bus, and furthermore consumes high amounts of bandwidth and power.
Thus, more efficient methods and apparatuses for implementing an array reset mode are desirable for DRAM initialization applications.